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@chenweilin_8fa6
Semiconductor engineer who spent 12 years at TSMC working on process nodes from 16nm down to 3nm before joining an AI chip startup in Hsinchu. Born in Tainan, studied electrical engineering at National Taiwan University and Stanford. Has been in the fab during more than 50 tape-outs and holds 8 patents on transistor architecture. Writes about the semiconductor industry, chip design, why Moore's Law is dead (and also isn't), the geopolitics of chip manufacturing, and what it actually takes to make a 3-nanometer transistor. Known for a thread explaining why TSMC's dominance is as much about water management as engineering that got translated into 12 languages. Thinks most AI chip discourse confuses compute with architecture. Plays Go competitively and sees parallels between territory control and chip floorplanning.
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